added logic to increment addr

fpgamatrix.vhd

@@ -27,8 +27,10 @@ entity fpgamatrix is
 end entity fpgamatrix;
 
 architecture fpgamatrix_arch of fpgamatrix is
+	constant maxaddr : natural := 7;
+	
 	signal ledclk : std_logic;
-	signal addr : std_logic_vector(3 downto 0);
+	signal addr : natural range 0 to maxaddr;
 	
 	component mypll is
 		Port (
@@ -38,21 +40,25 @@ architecture fpgamatrix_arch of fpgamatrix is
 	end component mypll;
 	
 	component ledctl is
+		Generic (
+			maxaddr : natural
+		);
 		Port (
 			ledclk : in std_logic;
 			ledoutclk : out std_logic;
-			addr : out std_logic_vector(3 downto 0);
+			addr : out natural range 0 to maxaddr;
 			latch : out std_logic
 		);
 	end component ledctl;
 		
 	component ledgen is
 		Generic (
+			maxaddr : natural;
 			topdown : topdown_type
 		);
 		Port (
 			clk : in std_logic;
-			addr : in std_logic_vector(3 downto 0);
+			addr : in natural range 0 to maxaddr;
 			r : out std_logic;
 			g : out std_logic;
 			b : out std_logic
@@ -66,6 +72,9 @@ begin
 		);
 	
 	ledctl_inst : ledctl
+		Generic Map (
+			maxaddr => maxaddr
+		)
 		Port Map (
 			ledclk => ledclk,
 			addr => addr,
@@ -74,6 +83,7 @@ begin
 		
 	ledgen_top : ledgen
 		Generic Map (
+			maxaddr => maxaddr,
 			topdown => top
 		)
 		Port Map (
@@ -86,6 +96,7 @@ begin
 		
 	ledgen_down : ledgen
 		Generic Map (
+			maxaddr => maxaddr,
 			topdown => down
 		)
 		Port Map (
@@ -103,6 +114,6 @@ begin
 	
 	assignaddr : process(addr) is
 	begin
-		outaddr <= addr;
+		outaddr <= std_logic_vector(to_unsigned(addr, 4));
 	end process assignaddr;
 end fpgamatrix_arch;

ledctl.vhd

@@ -3,14 +3,47 @@ use IEEE.STD_LOGIC_1164.ALL;
 use IEEE.numeric_std.all;
 
 entity ledctl is
+	Generic (
+		maxaddr : natural
+	);
 	Port (
 		ledclk : in std_logic;
 		ledoutclk : out std_logic;
-		addr : out std_logic_vector(3 downto 0);
+		addr : out natural range 0 to maxaddr;
 		latch : out std_logic
 	);
 end entity ledctl;
 
 architecture ledctl_arch of ledctl is
+	constant lednum : natural := 32;
+	
+	signal newline : std_logic := '0';
 begin
-end architecture ledctl_arch;
\ No newline at end of file
+	ledcounter : process(ledclk) is
+		variable curled : natural range 0 to lednum;
+	begin
+		if falling_edge(ledclk) then
+			newline <= '0';
+			curled := curled + 1;
+			if curled = lednum then
+				curled := 0;
+				newline <= '1';
+			end if;
+		end if;
+	end process ledcounter;
+	
+	addrcounter : process(newline) is
+	variable curaddr : natural range 0 to maxaddr + 1 := 0;
+	begin
+		if rising_edge(newline) then
+			curaddr := curaddr + 1;
+			if curaddr = maxaddr + 1 then
+				curaddr := 0;
+			end if;
+			addr <= curaddr;
+		end if;
+	end process addrcounter;
+end architecture ledctl_arch;
+
+
+

ledgen.vhd

@@ -7,11 +7,12 @@ use mylib.mytypes.all;
 
 entity ledgen is
 	Generic (
+		maxaddr : natural;
 		topdown : topdown_type
-		);
+	);
 	Port (
 		clk : in std_logic;
-		addr : in std_logic_vector(3 downto 0);
+		addr : in natural range 0 to maxaddr;
 		r : out std_logic;
 		g : out std_logic;
 		b : out std_logic